1. Field of the Invention
The present invention relates to a capacitor to be incorporated in a wiring substrate, a method for manufacturing the capacitor, and the wiring substrate.
2. Description of the Related Art
In accordance with the progress of an integrated circuit technology of recent years, the actions of a semiconductor chip becomes higher and higher in speeds. Accordingly, noises may be superposed on power source lines or the like to cause malfunctions. Thus, the noises are removed by mounting a capacitor on the upper face or lower face of a wiring substrate to mount the semiconductor chip.
In the aforementioned method, however, after completion of the wiring substrate, it is necessary to mount the capacitor separately, so that the process number increases. It is also necessary to retain such an area in advance as to mount the capacitor on the wiring substrate, so that the degree of freedom for other electronic parts is lowered. Due to the restrictions by other wires, the wiring distance between the capacitor and the semiconductor chip is elongated to increase the wiring resistance or inductance.
With these in mind, it has been proposed (as referred to JP-A-2005-39243, for example) to incorporate the capacitor in the wiring substrate. Here, the capacitor may be incorporated in the opening of a core substrate forming the core of the wiring substrate. In this case, the gap between the core substrate and the capacitor is filled with a resin filler so as to fix the capacitor in the core substrate. Since, however, the side faces of the capacitor are made mainly from ceramics, the adhesion properties between the capacitor and the resin filler are so low that the reliability cannot be sufficiently retained.
Moreover, a thermal stress is concentrated either in the resin filler between the core substrate in the wiring substrate and the capacitor or in the insulating layers near the capacitor in the wiring substrate by the heat which is generated at the action time of the semiconductor chip. As a result, cracks may be caused in the resin filler or the insulating layers.
Against these problems, it has been proposed (as referred to JP-A-2004-172305, for example) to form rounded portions having a radius of curvature of 0.01 to 0.1 mm between the side faces and the upper and lower faces of the capacitor. Since, however, the rounded portions are formed by a polishing method after the capacitor was sintered, the dielectric layers after sintered are worked to require long working time periods and high costs.
The capacitor to be incorporated in the wiring substrate, as described in JP-A-2005-39243, is manufactured by forming a laminate including a plurality of dielectric layers laminated and internal electrode layers arranged between the dielectric layers, and by sintering the laminate. However, a warpage may occur at the sintering time. Therefore, it has been proposed to prepare an assembly of the capacitor and to divide the assembly into capacitors after sintered.
Here in the capacitor to be incorporated in the wiring substrate, it is necessary to form external electrode layers to be electrically connected with the wiring lines formed on the wiring substrate. On these external electrode layers, there may be formed plated external electrode layers for improving the adhesion properties with the insulating layers of the buildup layers, and plated films for preventing the oxidation of the external electrode layers. These plated films are formed at present by an electroless plating method.
However, it takes a long time to form the plated films by the electroless plating method. In case the distance between the external electrode layers is so short as 150 μm, the external electrode layers may be connected by the plated films and may be electrically shorted.
Thus, it has been proposed to form the plated films not by the electroless plating method but by an electrolytic plating method. In case, however, the aforementioned capacitor assembly is to be manufactured, the break trenches for dividing the capacitor have to be formed in the assembly. Between the adjoining capacitors, therefore, the external electrode layers are spaced from each other across the break trenches. When the plated films are to be formed by the electrolytic plating method, therefore, the electrodes or the like have to be brought into contact for every external electrode layers so that the plated films cannot be efficiently formed by the electrolytic plating method.
There has been disclosed a technique (e.g., JP-A-61-276396), in which the boundaries between the body having the wiring pattern and a disposal plate are perforated, and in which the wiring pattern is electrolytically plated. However, the perforations in this technique are just for dividing the body and the disposal plate and have no relation to the electrolytic plating method.